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Add ESP8266 core v2.6.2 (#905)

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* Add ESP8266 core v2.6.2

* Upstream ESP8266 Wifi fixes

* Replace disable_interrupt with InterruptLock C++ class

* Update code to use InterruptLock

* Lint

* Update dht.cpp

* Improve InterruptLock docs, mark as ICACHE_RAM_ATTR

* Fixes
This commit is contained in:
Otto Winter
2019-12-04 19:30:10 +01:00
committed by GitHub
parent bba6d6897d
commit 7a6df38515
12 changed files with 291 additions and 180 deletions
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esphome/components/dallas/esp_one_wire.cpp
+13 -13
View File
@@ -12,7 +12,7 @@ const int ONE_WIRE_ROM_SEARCH = 0xF0;
ESPOneWire::ESPOneWire(GPIOPin *pin) : pin_(pin) {}
bool HOT ESPOneWire::reset() {
bool HOT ICACHE_RAM_ATTR ESPOneWire::reset() {
uint8_t retries = 125;
// Wait for communication to clear
@@ -39,7 +39,7 @@ bool HOT ESPOneWire::reset() {
return r;
}
void HOT ESPOneWire::write_bit(bool bit) {
void HOT ICACHE_RAM_ATTR ESPOneWire::write_bit(bool bit) {
// Initiate write/read by pulling low.
this->pin_->pin_mode(OUTPUT);
this->pin_->digital_write(false);
@@ -60,7 +60,7 @@ void HOT ESPOneWire::write_bit(bool bit) {
}
}
bool HOT ESPOneWire::read_bit() {
bool HOT ICACHE_RAM_ATTR ESPOneWire::read_bit() {
// Initiate read slot by pulling LOW for at least 1µs
this->pin_->pin_mode(OUTPUT);
this->pin_->digital_write(false);
@@ -76,43 +76,43 @@ bool HOT ESPOneWire::read_bit() {
return r;
}
void ESPOneWire::write8(uint8_t val) {
void ICACHE_RAM_ATTR ESPOneWire::write8(uint8_t val) {
for (uint8_t i = 0; i < 8; i++) {
this->write_bit(bool((1u << i) & val));
}
}
void ESPOneWire::write64(uint64_t val) {
void ICACHE_RAM_ATTR ESPOneWire::write64(uint64_t val) {
for (uint8_t i = 0; i < 64; i++) {
this->write_bit(bool((1ULL << i) & val));
}
}
uint8_t ESPOneWire::read8() {
uint8_t ICACHE_RAM_ATTR ESPOneWire::read8() {
uint8_t ret = 0;
for (uint8_t i = 0; i < 8; i++) {
ret |= (uint8_t(this->read_bit()) << i);
}
return ret;
}
uint64_t ESPOneWire::read64() {
uint64_t ICACHE_RAM_ATTR ESPOneWire::read64() {
uint64_t ret = 0;
for (uint8_t i = 0; i < 8; i++) {
ret |= (uint64_t(this->read_bit()) << i);
}
return ret;
}
void ESPOneWire::select(uint64_t address) {
void ICACHE_RAM_ATTR ESPOneWire::select(uint64_t address) {
this->write8(ONE_WIRE_ROM_SELECT);
this->write64(address);
}
void ESPOneWire::reset_search() {
void ICACHE_RAM_ATTR ESPOneWire::reset_search() {
this->last_discrepancy_ = 0;
this->last_device_flag_ = false;
this->last_family_discrepancy_ = 0;
this->rom_number_ = 0;
}
uint64_t HOT ESPOneWire::search() {
uint64_t HOT ICACHE_RAM_ATTR ESPOneWire::search() {
if (this->last_device_flag_) {
return 0u;
}
@@ -196,7 +196,7 @@ uint64_t HOT ESPOneWire::search() {
return this->rom_number_;
}
std::vector<uint64_t> ESPOneWire::search_vec() {
std::vector<uint64_t> ICACHE_RAM_ATTR ESPOneWire::search_vec() {
std::vector<uint64_t> res;
this->reset_search();
@@ -206,12 +206,12 @@ std::vector<uint64_t> ESPOneWire::search_vec() {
return res;
}
void ESPOneWire::skip() {
void ICACHE_RAM_ATTR ESPOneWire::skip() {
this->write8(0xCC); // skip ROM
}
GPIOPin *ESPOneWire::get_pin() { return this->pin_; }
uint8_t *ESPOneWire::rom_number8_() { return reinterpret_cast<uint8_t *>(&this->rom_number_); }
uint8_t ICACHE_RAM_ATTR *ESPOneWire::rom_number8_() { return reinterpret_cast<uint8_t *>(&this->rom_number_); }
} // namespace dallas
} // namespace esphome